What's New v17.0: Support for variable sized blocks
The fast Fourier transform (FFT) Intel® FPGA IP core is a high-performance, highly parameterizable FFT processor. The FFT function implements a radix-2/4 decimation-in-frequency (DIF) FFT algorithm for transform lengths of 2m where 6 ≤ m ≤ 14, internally using a block-floating-point architecture to maximize signal dynamic range in the transform calculation.
The FFT Intel FPGA IP core accepts, as input, a complex data vector of length N (in two’s complement format) and outputs the transform-domain complex vector in natural order. An accumulated block exponent is output to indicate any data scaling that has occurred during the transform to maintain precision and maximize the internal signal-to-noise ratio. Transform direction is specifiable on a per-block basis via an input port.