In an increasingly competitive market, hardware designers must focus time and effort on designs that enhance and differentiate a product, rather than on designs that implement industry-standard protocols or interfaces. Drop-in intellectual property (IP) cores have, therefore, become a popular way to fulfill the need for standard protocol and interface logic. To ensure that an IP core meets the functional requirements of a complex protocol or the critical I/O timing requirements of an interface, hardware verification must be performed.
Intel® awards the interoperability-tested or I-Tested certification to MegaCore® or Intel FPGA Megafunction Partners Program (AMPPSM) IP cores that have been verified in an Intel FPGA on an evaluation board with the ASSPs, hardware components, or test equipment necessary to ensure interoperability according to the necessary protocols.
Visit the online IP catalog for an up-to-date list of I-Tested IP cores.
I-Tested Core Deliverables
Intel requires that the IP core have the following deliverables in order to achieve I-Tested certification:
Successful Interoperability Testing in an Altera FPGA on an Evaluation Board
The board must include other industry-standard components and/or off-board interfaces (e.g. to standard hardware test equipment) to verify the protocol managed by the IP core. The core must be tested at least with typical configurations and parameters and with typical performance targets.
Description of Hardware Platform
Core documentation must include a description of the hardware platform used, including the types of components used.
Documentation of Interoperability Test Process
Core documentation must include descriptions of the tests performed. Details of test results may also be given, as appropriate.