Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

ID 683532
Date 8/05/2019
Public
Document Table of Contents

1. Introduction

Updated for:
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.2

The Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA features a QSFP+ network port that can be configured for either 4x10GBASE-SR or 40GBASE-SR4 operation. This guide documents how to design for the network port feature in an accelerator functional unit (AFU) design and how to provision it from the host using the Open Programmable Acceleration Engine (OPAE) driver and tools. The following figure overviews the Intel® PAC with Intel® Arria® 10 GX FPGA OPAE hardware platform.

Figure 1. Overview of the Intel® PAC with Intel® Arria® 10 GX FPGA

Host/client-side network packet data passes through the Core Cache Interface (CCI-P) to MAC/PHY IP implemented in the AFU, which interfaces to the high speed serial interface (HSSI) PHY in the FPGA interface manager (FIM) through the hssi device interface. The host configures the HSSI PHY and retrieves MAC address information using the OPAE kernel driver. The OPAE kernel driver communicates with the HSSI Controller in the FIM through the FPGA management engine (FME) mailbox, to initiate configuration and requests for information (including the MAC address).

For detailed information about the FME, refer to the Intel Acceleration Stack Quick Start Guide for Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA.