AN647: Single-Port Triple Speed Ethernet and On-Board PHY Chip Reference Design
Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design
The Single-Port Triple-Speed Ethernet and On-Board PHY Chip reference designs demonstrate Ethernet operations of the Altera® Triple-Speed Ethernet IP core with on-board Marvell 88E1111 PHY chips. In these reference designs, the Triple-Speed Ethernet IP core connects to the on-board PHY chip through either the Reduce Gigabit Media Independent Interface (RGMII) or the Serial Gigabit Media Independent Interface (SGMII).
- Minimal hardware requirement for a complete test.
- Implementation of one Triple-Speed Ethernet IP core instance supporting 10/100/1000-Mbps Ethernets operations with RGMII or SGMII with auto-negotiation.
- Support for programmable test parameters such as number of packets, packet length, source and destination MAC addresses, and payload-data type.
- Support for sequential random bursts test that enables the configuration of each burst for the number of packets, payload-data type, and payload size.
- Demonstration of Ethernet packets transmission and reception through internal loopback path at the maximum theoretical data rates without errors.
- Support for gathering throughput statistics.
- Support for System Console user interface.
System Architecture
Design Components
Component | Description |
---|---|
Phase-Locked Loop (PLL) Core |
|
JTAG to Avalon Master Bridge Core |
|
Triple-Speed Ethernet IP Core |
|
Ethernet Packet Generator |
This Qsys custom component generates Ethernet packets. Refer to Ethernet Packet Generator for more information. |
Ethernet Packet Monitor |
This Qsys custom component verifies the payload of all receive packets, indicates the validity of the packets, and collects statistics about each packet, such as the number of bytes received. Refer to Ethernet Packet Monitor for more information. |
Error Adapter |
Note: Not applicable for Arria 10 designs.
|
Avalon-ST Multiplexer |
Note: Not applicable for Arria 10 designs.
|
Avalon-ST Splitter |
Note: Not applicable for Arria 10 designs.
|
Ethernet Packet Generator
Component | Description |
---|---|
Ethernet Packet Generation Block |
|
CRC Generator |
|
Avalon-MM Registers |
|
Shift Register (RAM-based) IP Core | The Shift Register IP core implements a shift register with
taps.
Refer to the RAM-Based Shift Register IP Core User Guide for more information. |
Ethernet Packet Monitor
Component | Description |
---|---|
CRC Checker |
|
Avalon-MM Registers |
|
Interface Signals
Clock and Reset Signals
Signal | Description |
---|---|
clk_clk | Reference design clock. The clock is derived from the PLL. |
triple_speed_ethernet_0_pcs_mac_rx_clock_connection_clk | RGMII receive clock. The clock is sourced from the on-board PHY chip. |
triple_speed_ethernet_0_pcs_mac_tx_clock_connection_clk | RGMII transmit clock. The clock is sourced from the clock multiplexer which is sourced from the PLL. |
reset_reset_n | Single reset signal for all logic in the reference design. |
Signal | Description |
---|---|
clk_clk | Reference design clock. The clock is derived from the PLL. |
triple_speed_ethernet_0_pcs_ref_clk_clock_connection_clk | Reference clock for the transceiver. The clock is sourced from the 125-MHz oscillator. |
reset_reset_n | Single reset signal for all logic in the reference design. Connect this reset signal to the RESET push button (USER_PB0). |
Triple-Speed Ethernet Component Signals
Signal | Description |
---|---|
triple_speed_ethernet_0_mac_rgmii_connection_rgmii_in | RGMII receive data bus. Connect this bus to the on-board PHY chip. |
triple_speed_ethernet_0_mac_rgmii_connection_rx_control | RGMII receive control output signal. Connect this signal to the on-board PHY chip. |
triple_speed_ethernet_0_mac_rgmii_connection_rgmii_out | RGMII transmit data bus. Connect this bus to the on-board PHY chip. |
triple_speed_ethernet_0_mac_rgmii_connection_tx_control | RGMII transmit control output signal. Connect this signal to the on-board PHY chip. |
Signal | Description |
---|---|
triple_speed_ethernet_0_serial_connection_rxp_0 | SGMII receive serial data bus. Connect this bus to the on-board PHY chip. |
triple_speed_ethernet_0_serial_connection_txp_0 | SGMII transmit serial data bus. Connect this bus to the on-board PHY chip. |
Base Addresses and Configuration Registers
Base Address | Name | Description |
---|---|---|
0x00000000 | triple_speed_ethernet_0 | Triple-Speed Ethernet |
0x00000400 | st_mux_2_to_1_0 | Avalon-ST Multiplexer
Note: Not applicable for Arria 10 designs.
|
0x00000800 | eth_mon_0 | Ethernet Packet Monitor |
0x00000C00 | eth_gen_0 | Ethernet Packet Generator |
Ethernet Packet Generator Configuration Registers
Byte Offset | Register | Bit Number | Bit Name | R/W | H/W Reset | Description |
---|---|---|---|---|---|---|
0x00 | number_packet | 31:0 | – | RW | 0x00 | Specifies the total number of packets to be generated. |
0x04 | config_setting | 0 | LENGTH_SEL | RW | 0x00 |
0: Fixed packet length 1: Random packet length |
14:1 | PKT_LENGTH | RW | 0x00 |
Specifies the fixed packet length. Valid values are between 24 to 9,600. Applicable only when you set bit 0 of this register to 0. |
||
15 | PATTERN_SEL | RW | 0x00 |
Specifies the data pattern for the random packet length. 0: Incremental—data starts from zero and increments by 1 in subsequent bytes. 1: Random. |
||
31:16 | – | – | – | Reserved. | ||
0x08 | operation | 0 | START | RW | 0x00 | Set this bit to 1 to trigger packet generation. This bit clears as soon as packet generation starts. |
1 | STOP | RW | 0x00 | Set this bit to 1 to stop packet generation. The generator completes the current packet before termination packet generation. | ||
2 | TX_DONE | RO | 0x00 | A value of 1 indicates that the packet generator completes generating the total number of packets specified in the number_packet register. This bit clears each time packet generation triggers. | ||
31:3 | – | – | – |
Reserved. |
||
0x10 | source_addr0 | 31:0 | – | RW | 0x00 |
6-byte MAC address.
For example, if the source MAC address is 00-1C-23-17-4A-CB, you
get the following assignments:
|
0x14 | source addr1 | 31:0 | – | RW | 0x00 | |
0x18 | destination_addr0 | 31:0 | – | RW | 0x00 | |
0x1C | destination_addr1 | 31:0 | – | RW | 0x00 | |
0x24 | packet_tx_count | 31:0 | – | – | – |
Keeps track of the number of packets the generator successfully transmits. This register clears each time packet generation triggers. |
0x30 | rand_seed0 | 31:0 | – | RW | 0x00 |
The lower 32 bits of the random seed. Occupies bits 31:0 of the PBRS generator when you set the data pattern to random (bit 15 of the configuration register). |
0x34 | rand_seed1 | 31:0 | – | RW | 0x00 |
The middle 32 bits of the random seed. Occupies bits 63:32 of the PBRS generator when you set the data pattern to random (bit 15 of the configuration register). |
0x38 | rand_seed2 | 31:0 | – | RW | 0x00 |
The upper 32 bits of the random seed. Occupies bits 91:64 of the PBRS generator when you set the data pattern to random (bit 15 of the configuration register). |
Ethernet Packet Monitor Configuration Registers
Byte Offset | Register | Bit Number | Bit Name | R/W | H/W Reset | Description |
---|---|---|---|---|---|---|
0x00 | number_packet | 31:0 | – | RO | 0x00 | Total number of packets the monitor expects to receive. |
0x04 | packet_rx_ok | 31:0 | – | RO | 0x00 | Total number of good packets received. |
0x08 | packet_rx_error | 31:0 | – | RO | 0x00 |
Total number of packets received with error. |
0x0C | byte_rx_count_0 | 31:0 | – | RO | 0x00 |
64-bit counter that keeps track of the total number of bytes received.
Read byte_rx_count_0 followed by byte_rx_count_1 in the subsequent cycle to get an accurate count. |
0x10 | byte_rx_count_1 | 31:0 | – | RO | 0x00 | |
0x14 | cycle_rx_count_0 | 31:0 | – | RO | 0x00 |
64-bit counter that keeps track of the total number of cycles the monitor takes to receive all packets..
Read byte_rx_count_0 followed by byte_rx_count_1 in the subsequent cycle to get an accurate count. |
0x18 | cycle_rx_count_1 | 31:0 | – | RO | 0x00 | |
0x1C | rx_control_status | 0 | START | RW | 0x00 | Set this bit to 1 to start packet reception. This bit clears when packet reception starts. |
1 | STOP | RW | 0x00 | Set this bit to 1 to stop packet reception. This bit clears each time packet reception starts. | ||
2 | RX_DONE | RO | 0x00 | A value of 1 indicates that the packet monitor has received the total number of packets specified in the number_packet register. | ||
3 | CRCBAD | RO | 0x00 |
A value of 1 indicates CRC error in the current packet received by the monitor. |
||
9:4 | RX_ERR | RO | 0x00 |
Receive error status. The rx_err[] signal of the Triple-Speed Ethernet IP core maps to this register. |
||
31:10 | – | – | – |
Reserved. |
Running the Reference Designs
To run the tests, download and unzip the reference design files to your local directory.
Components | File | Description |
---|---|---|
Top Level Design File | top.v | Top-level entity file of the reference design for verification in the hardware. |
top_out.sdc | Quartus® Prime SDC constraint file for use with the TimeQuest timing analyzer. | |
qsys_top.qsys | Qsys file of the reference design. | |
pll.v | The IP-generated PLL file. | |
Ethernet Generator | eth_gen_hw.tcl | Qsys custom component which generates Ethernet packets. |
eth_gen.v | The top level file of the Ethernet Packet Generator. | |
prbs23.v | Module to generate Pseudo-Random Bit Sequence 23 data. | |
shiftreg_data.v | RAM-based shift register to delay transmit packet payload sending to Triple-Speed Ethernet TX FIFO interface for CRC checksum merging at EOP. | |
shiftreg_ctrl.v | RAM-based shift register to store and delay control signals. | |
crcgen_dat32.v | Module to generate checksum CRC32. | |
Ethernet Monitor | eth_mon_hw.cl | Qsys custom component which verifies the payload of all receive packets. |
eth_mon.v | Top level file of the Ethernet Packet Monitor. | |
crcchk_dat32.v | Module to verify the data payload of the received packets. | |
CRC Generator/Checke | crc32.sdc | Quartus® Prime SDC constraint file for use with the TimeQuest timing analyzer. |
crc32_chk.v | Top level file of the CRC 32 checker. | |
crc32_gen.v | Top level file of the CRC 32 generator. | |
avalon_st_to_crc_if_bridge.v | Module to convert the Avalon-ST signal to the CRC 32 calculator input signal. | |
byte_endian_converter.v | Module to convert the input data byte to big or little endian. | |
crc32_calculator.v | Module to calculate the crc32 checksum for the incoming data. | |
crc_checksum_aligner.v | Module to align the checksum with crc_valid signal. | |
crc_comparator | Module to compare the checksum of the receiving packet with the Ethernet CRC 32 residue value. | |
Avalon-St Multiplexer
(not applicable for Arria 10 designs) |
st_mux_2_to_1_hw.tcl | The Qsys custom component accepts data on its two Avalon-ST sink interfaces, and multiplexes the data for transmission on its Avalon-St source interface. |
st_mux_2_to_1.v | ||
st_mux.v | LPM_MUX IP core file. | |
Avalon St-Splitter
(not applicable for Arria 10 designs) |
aso_splitter_hw.tcl | The Qsys custom component accepts data on its Avalon-ST sink interface and splits the data for transmission on its two Avalon-ST source interfaces. |
aso_splitter.v | ||
Error Adaptor
(not applicable for Arria 10 designs) |
error_adapter2_hw.tcl | The Qsys custom component connects mismatched Avalon-ST source and sink interfaces. |
error_adapter2.tcl |
Hardware and Software Requirements
The reference designs require the following hardware and software:
- Arria 10 GX, Arria V GX, or Stratix V GX, or Stratix IV GX FPGA Development Kit
- USB-Blaster® or ByteBlaster® download cable
- External Ethernet packet generator (only for Avalon-ST reverse loopback test)
- Ethernet cable assembly (only for Avalon-ST reverse loopback test)
-
Quartus® Prime version 15.0 or later
- USB-Blaster or ByteBlaster driver
- Qsys system
- System Console
Internal MAC Loopback Test
- Connect the programming cable to the JTAG connection port.
- Connect the board to the power supply input.
-
Set up the System Console.
- Open Qsys.
-
On the Tools menu, click System Console.
The System Console is a debugging tool that provides you with Tcl scripts to perform low-level hardware debugging and run tests on your reference designs. The console communicates to the hardware components instantiated into your Qsys system reference designs through the JTAG to Avalon Master Bridge.
- Open the config.tcl script and set LOOP_ENA to 1 to enable the MAC loopback mode.
-
Type the following command to start the MAC and PHY configurations in the
System Console:
source config.tclFor more information, refer to Configuration Script.The System Console displays the copper link connection status and the PHY’s operating speed and mode. Verify that the console displays the correct configurations
-
Open and edit the eth_gen_start.tcl script.
For more information, refer to Ethernet Packet Generator Script.
-
Type the following command to start generating Ethernet packets:
source eth_gen_start.tclThe Ethernet Packet Monitor automatically starts when you start the Ethernet Packet Generator.
- When the monitor receives all the Ethernet packets, the System Console displays the loopback test result.
- If the monitor receives packets with error, the console displays the total number of packets received with error and the type of error for each packet.
-
Type the following command to view the MAC statistic counters:
source tse_stat_read.tcl
Avalon-ST Reverse Loopback Test
- Using the Ethernet cable assembly, connect the external generator to the RJ-45 port of the FPGA development board.
- Connect the programming cable to the JTAG connection port.
- Connect the board to the power supply input (J4).
-
Set up the System Console.
- Open Qsys.
-
On the Tools menu, click System Console.
The System Console is a debugging tool that provides you with Tcl scripts to perform low-level hardware debugging and run tests on your reference designs. The console communicates to the hardware components instantiated into your Qsys system reference designs through the JTAG to Avalon Master Bridge.
-
Open the config.tcl script
and set LOOP_ENA to 0 to disable the MAC
loopback mode.
For more information, refer to Configuration Script.
-
Type the following command to start the MAC and PHY
configurations in the System Console:
source config.tclThe System Console displays the copper link connection status and the PHY’s operating speed and mode. Verify that the console displays the correct configurations
- Start sending Ethernet packets from the external packet generator to the FPGA development board and verify that the packets are correctly looped back to the external packet generator.
-
Type the following command to view the MAC statistic
counters:
source tse_stat_read.tcl
Tcl Script
Configuration Script
- MAC configuration setting to configure the MAC registers.
- PCS configuration setting to configure the PCS registers.
- Marvell PHY configuration setting to configure the on-board PHY chip
registers.
Parameter Description PHY_ENABLE To enable or disable the on-board PHY chip. PHY_ETH_SPEED To select the PHY’s operating speed. PHY_ENABLE_AN To enable or disable auto-negotiation on the PHY. PHY_COPPER_DUPLEX To select the PHY’s operating mode.Statistic Counter Script PHY_LOOPBACK To enable or disable the on-board PHY serial loopback.
The tse_stat_read.tcl script reads the values of the MAC statistic counters after you execute the reference designs.
Ethernet Packet Generator Script
You can use any text editor to configure the following registers in eth_gen_start.tcl script.
number_packet | To set the total number of packets to be generated by the packet generator. |
eth_gen | To enable or disable the packet generator. |
length_sel | To select fixed or random packet length. |
pkt_length | To set the fixed packet length. The packet length can be a value between 24 to 9,600 bytes. |
pattern_sel | To select the data pattern for the random packet length. |
rand_seed | To set the initial random seed for the PRBS generator. This parameter is only valid when you select random packet length. |
source_addr | To set the source MAC address. |
destination_addr | To set the destination MAC address. |
JTAG Connection Port for Altera Devices
Device | JTAG Connection Port |
---|---|
Arria 10 GX | J3 |
Arria V GX | J14 |
Stratix V GX | J7 |
Stratix IV GX | J7 |
Document Revision History
Date | Version | Changes |
---|---|---|
December 2015 | 2015.12.14 |
|
December 2012 | 2012.12.03 | Added device support and restructured reference design topic. |
Sept 2011 | 2011.09.23 | Updated the link to the design example download page. |
June 2011 | 2011.06.17 | Initial release. |