AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

ID 683803
Date 7/31/2018
Public

Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

Bus LVDS (BLVDS) extends the capability of LVDS point-to-point communication to multipoint configuration. Multipoint BLVDS offers an efficient solution for multipoint backplane applications.
Table 1.  BLVDS Implementation Support in Intel® FPGA DevicesYou can implement BLVDS interfaces in these Intel® devices using the listed I/O standards.
Series Family I/O Standard
Stratix® Intel® Stratix® 10
  • Differential SSTL-18 Class I
  • Differential SSTL-18 Class II
Stratix® V
  • Differential SSTL-2 Class I
  • Differential SSTL-2 Class II
Stratix® IV
Stratix® III
Arria® Intel® Arria® 10
  • Differential SSTL-18 Class I
  • Differential SSTL-18 Class II
Arria® V
  • Differential SSTL-2 Class I
  • Differential SSTL-2 Class II
Arria® II
Cyclone® Intel® Cyclone® 10 GX
  • Differential SSTL-18 Class I
  • Differential SSTL-18 Class II
Intel® Cyclone® 10 LP BLVDS
Cyclone® V
  • Differential SSTL-2 Class I
  • Differential SSTL-2 Class II
Cyclone® IV BLVDS
Cyclone® III LS
Cyclone® III
MAX® Intel® MAX® 10 BLVDS
Note: The programmable drive strength and slew rate features in these devices allow you to customize your multipoint system for maximum performance. To determine the maximum data rate supported, perform a simulation or measurement based on your specific system setup and application.