AN 706: Routing HPS Peripheral Signals to the FPGA External Interface

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AN-706 | 2018.05.07

AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface

The Altera Cyclone^® V and Arria^® V SoC device families integrate an Arm^® Cortex^® -A9-based hard processor system (HPS) consisting of processor, peripherals, and memory interface with the FPGA fabric using a high-bandwidth interconnect backbone. The Cyclone^® V HPS interface provides up to 67 I/O pins to share with multiple peripherals through sets of configurable multiplexers. The Arria^® V HPS interface provides up to 71 I/O pins.

This application note describes the steps required to route an HPS peripheral through the FPGA interface using Platform Designer (Standard) and Intel^® Quartus^® Prime Standard Edition software. A simple design example is included to demonstrate exporting HPS EMAC0 and I2C0 peripheral signals to the FPGA interface using a Cyclone^® V SoC Development Kit.

Cyclone V and Arria V HPS Peripherals That Support Routing to the FPGA

The following types of Cyclone^® V and Arria^® V HPS peripherals are capable of routing to the FPGA fabric:

Ethernet Media Access Controller (EMAC)
Quad Serial Peripheral Interface (QSPI)
Secure Digital/Multimedia Card (SD/MMC)
Serial Peripheral Interface (SPI)
Universal Asynchronous Receiver/Transmitter (UART)
Inter-Integrated Circuit (I²C)
Controller Area Network (CAN)¹

In many cases, routing the HPS IP signals to the FPGA external interface allows more signals to be exposed.

Table 1. Peripherals that Support Signal Routing from the HPS Domain to FPGA Domain. The following table lists the interface type that is available depending on whether the IP interface is pinned out in the HPS domain or the FPGA domain.
Peripherals	Interface Description
	HPS Domain	FPGA Domain
EMAC	RGMII Interface	GMII Interface
QSPI	Standard QSPI interface with four slave select signals	Standard QSPI interface with four slave select signals achieved by connecting exported signals to bidirectional buffers
SD/MMC	Standard SD/MMC interface with up to 8-bit data bus	Standard SD/MMC interface, including: Up to 8-bit data bus Card detect interface Card interrupt Voltage switching Power enable Reset ²
SPI Master	MOSI/MISO SPI interface configurable to single or dual slaves	MOSI/MISO SPI interface with output enables that support up to four slaves; interface achieved by connecting exported signals to bidirectional buffers
SPI Slave	MOSI/MISO SPI interface configurable to single or dual slaves	MOSI/MISO SPI interface with output enables that support up to four slaves; interface achieved by connecting exported signals to bidirectional buffers
UART	Standard UART interface with flow control signals	Standard UART interface with flow control signals, including DTR and DSR; status and two user-defined output signals are also available
I²C	Standard I²C interface	Standard I²C interface achieved by connecting exported signals to a bidirectional buffer
CAN³	Standard CAN interface	Standard CAN interface

Refer to the following chapters of the Cyclone^® V Hard Processor System Technical Reference Manual for descriptions of each peripheral signal interface:

¹ The CAN interface is only available in the Cyclone^® V SoC device family.

² The SD/MMC controller does not directly support reset, voltage switching, card interrupts, power enable or write protect functions. However, you can connect these signals to general-purpose I/Os (GPIOs).

³ The CAN interface is only available in the Cyclone^® V SoC device family.

Design Example: Cyclone V HPS IP Interface to FPGA

This design example, based on the Golden System Reference Design (GSRD), uses the Cyclone^® V SoC development kit resources to demonstrate routing the Cyclone^® V HPS EMAC0 and I2C0 peripheral signals to the FPGA interface.

The Cyclone^® V HPS component provides up to two EMAC peripherals, which support 10/100/1000 Mbps operation. The Cyclone^® V SoC Development board is populated with a Micrel KSZ9021RN RGMII PHY that interfaces to the HPS domain and a Renesas uPD60620A MII Dual Port PHY that interfaces to the FPGA domain. The HPS and FPGA also share a common I²C bus to various on-board I²C slaves.

Figure 1. High-level Routing Layout of Cyclone^® V SoC Board Design Example

The following sections provide the necessary information to route the HPS peripherals to the FPGA interface, such as:

Prerequisites

This design example is based on the Cyclone^® V GSRD and tested with Intel^® Quartus^® Prime Standard Edition version 14.0. Refer to the links listed below and review the recommended material before starting with this design example.

Hardware Requirements

The hardware required for this design example is:

Cyclone^® V SoC Development Kit
RJ45 Ethernet cable
SD/MMC card preloaded with default GSRD image

Software Requirements

The software required for this design example is:

Intel^® Quartus^® Prime Standard Edition 14.0 and above
SoC EDS 14.0 and above
Factory default hardware template cv_soc_devkit_ghrd in SoC EDS 14.0

Design example files are provided in the AN 706 design example link and are listed in the table below.

Table 2. Required Software Files
File Name	Description
`ghrd_top.v`	Top level RTL file
`soc_system_timing.sdc`	Timing constraint file
`an706_de_pin_assignment.tcl`	Pin assignment script file
`preloader-mkpimage.bin`	Generated preloader binary targeted to this project
`u-boot.img`	Modified u-boot image for EMAC0
`socfpga.dtb`	Modified device tree for EMAC0 and I2C0

Getting Started

Make a copy of the Cyclone^® V Golden Hardware Reference Design (GHRD) from your Cyclone^® V SoC Development Kit installation location or download the latest Cyclone^® V GHRD design example from the Rocketboards website to your project location.
Download the AN 706 design files (an706-design-files.zip) provided.
Open the GHRD project within the Intel^® Quartus^® Prime Standard Edition software.

Generating the Initial HDL in Platform Designer (Standard)

In the Intel^® Quartus^® Prime Standard Edition navigation bar, select Tools > Platform Designer (Standard) .
In the Platform Designer (Standard) window, select File > Open > soc_system.qsys .
In the System Contents tab, double click on hps_0 to open the HPS Parameters window.

Figure 2. System Contents Window
On the Peripheral Pins tab, under the Ethernet Media Access Controller section, click on the EMAC0 pin pull-down and select FPGA. The EMAC0 mode pull-down automatically displays Full to indicate GMII mode. Select the EMAC1 pin pull-down as Unused.

Figure 3. Selecting FPGA for EMAC0 Pin in the HPS Parameters Window
On the Peripheral Pins tab, scroll down to the I2C Controllers section, click on the I2C0 pin pull-down and select FPGA. The I2C0 mode pull-down automatically displays Full.

Figure 4. Selecting FPGA for I2C0 Pin in the HPS Parameters Window
Return to the System Contents tab and in the Export column, double-click on the EMAC0 and I2C0 signal pins to export them as conduits.

Figure 5. Exporting Pins in System Contents Window

Select Generate > Generate HDL from the Platform Designer (Standard) menu bar. In the project directory, replace the top level RTL file, ghrd_top.v, with the generated Verilog file.

Platform Designer (Standard) exposes the following EMAC0 and I2C0 interfaces in the file:

Table 3. EMAC0 Signals in the FPGA Domain
Signal	Width	Direction	Description
emac0_phy_txd_o	8	Out	PHY Transmit Data
emac0_phy_txen_o	1	Out	PHY Transmit Data Enable
emac0_phy_txer_o	1	Out	PHY Transmit Error
emac0_phy_rxdv_i	1	In	PHY Receive Data Valid
emac0_phy_rxer_i	1	In	PHY Receive Error
emac0_phy_rxd_i	8	In	PHY Receive Data
emac0_phy_col_i	1	In	PHY Collision Detect
emac0_phy_crs_i	1	In	PHY Carrier Sense
emac0_gmii_mdo_o	1	Out	MDIO signal data out
emac0_gmii_mdo_o_e	1	Out	MDIO signal output enable
emac0_gmii_mdi_i	1	In	MDIO signal input
emac0_gmii_mdc_o	1	Out	Management Data Clock
emac0_clk_rx_i	1	In	PHY RX reference clock
emac0_clk_tx_i	1	In	PHY TX reference clock
emac0_phy_txclk_o	1	Out	Transmit clock output to the PHY
emac0_rst_clk_tx_n_o	1	Out	Transmit clock reset output to the FPGA interface
emac0_rst_clk_rx_n_o	1	Out	Receive clock reset output

Table 4. I2C0 Signals in the FPGA Domain
Signal	Width	Direction	Description
i2c0_out_data	1	Out	Outgoing I²C data enable
i2c0_sda	1	In	Incoming I²C data
i2c0_clk_clk	1	Out	Outgoing I²C clock enable
i2c0_scl_in_clk	1	In	Incoming I²C clock source

Top Level Routing

The top level RTL file defines the pin connections from the Cyclone^® V HPS EMAC0 to the Renesas MII PHY on the Cyclone^® V SoC development board.

Note: Because MII is a 4-bit data width protocol, connect only the lower 4-bits, emac0_phy_txd_o[3:0] andemac0_phy_rxd_i[3:0], of EMAC0's RX and TX interface from the FPGA.

Figure 6. Routing of the EMAC0 FPGA Interface to the On-board MII PHY

HPS I2C0 is routed through the FPGA interface and acts as a master to various on-board I²C slaves:

Two Octal Digital Power Supply Managers with EEPROM
LCD
RTC
EEPROM

Note: A bi-directional buffer, ALT_IOBUF, must be added in the design to connect the I²C signals to an external open drain IO. The buffer can be included by instantiating ALT_IOBUF in ghrd_top.v.

The following Verilog code shows the ALT_IOBUF instantiation for an I²C interface implemented through the FPGA:

ALT_IOBUF scl_iobuf (.i(1'b0), .oe(scl_o_e), .o(scl_o), .io(fpga_i2c_scl)); //declared bi-directional buffer for scl
ALT_IOBUF sda_iobuf (.i(1'b0), .oe(sda_o_e), .o(sda_o), .io(fpga_i2c_sda)); //declared bi-directional buffer for sda

Timing Constraint Configuration

Replace the soc_system_timing.sdc file in your project directory with the soc_system_timing.sdc file provided in the project folder. This new file is customized for the EMAC0 and I2C0 interface being tested on the Cyclone^® V SoC development board.

Adding Pin Assignments in Intel Quartus Prime Standard Edition

Copy an706_de_pin_assignment.tcl from the AN 706 design files into your project directory.
In the Intel^® Quartus^® Prime Standard Edition menu bar, select Tools > Tcl Scripts

In the Tcl Scripts window, choose an706_de_pin_assignment.tcl and select Run.

Figure 7. Selecting pin_assigment.tcl in the Tcl Scripts Window

The an706_de_pin_assignment.tcl script automatically assigns EMAC0 and I2C0 signal pins to their related FPGA pin location.

Table 5. Pin Assignments for EMAC0 and I2C0
Signal	Direction	Pin Location
`enet1_rx_clk`	Input	`PIN_Y24`
`enet1_rx_d[0]`	Input	`PIN_AB23`
`enet1_rx_d[1]`	Input	`PIN_AA24`
`enet1_rx_d[2]`	Input	`PIN_AB25`
`enet1_rx_d[3]`	Input	`PIN_AE27`
`enet1_rx_dv`	Input	`PIN_Y23`
`enet1_rx_error`	Input	`PIN_AE28`
`enet1_tx_clk_fb`	Input	`PIN_W25`
`enet1_tx_d[0]`	Output	`PIN_W20`
`enet1_tx_d[1]`	Output	`PIN_Y21`
`enet1_tx_d[2]`	Output	`PIN_AA25`
`enet1_tx_d[3]`	Output	`PIN_AB26`
`enet1_tx_en`	Output	`PIN_AB22`
`enet1_tx_error`	Output	`PIN_AG5`
`enet_dual_resetn`	Output	`PIN_AJ1`
`enet_fpga_mdc`	Output	`PIN_H12`
`enet_fpga_mdio`	Bidirectional	`PIN_H13`
`fpga_i2c_scl`	Bidirectional	`PIN_G7`
`fpga_i2c_sda`	Bidirectional	`PIN_F6`

Hardware Programming File Compilation and Generation

After the Platform Designer (Standard) system is set up, the top level RTL file updated, the related signal pin location assigned and timing constrained, the design can be compiled and the SOF programming file generated.

In the Intel^® Quartus^® Prime Standard Edition software navigation bar, select Processing > Start Compilation to generate the SOF programming file.

SD Card Image Updates

Update the default SD card image with the generated preloader binary, u-boot image file and DTB file following the steps described below:

With your Linux machine, prepare the SD card by following the information in GSRD-Booting Linux Using Prebuilt SD Card Image. Untar the sd_image.bin.tar.gz file and program the image file, sd_image.bin into the SD card.
Replace the preloader-mkpimage.bin, u-boot.img and socfpga.dtb in the SD card.

Note: Information provided regarding SD card changes, preloader and Linux software file changes and preloader generation are applicable to this reference design only.

Preloader Generation

Because this design example modifies the default GHRD Platform Designer (Standard) file, it is essential to re-generate the preloader with the preloader generator.

U-boot Setup

Go to file location u-boot-socfpga/include/configs/socfpga_cyclone.h. The EMAC0 parameters associated with the interface speed must be configured to MII in the socfpga_cyclone.h file in the u-boot source. Change the #define for CONFIG_EMAC_BASE and CONFIG_PHY_INTERFACE_MODE to the following:

#define CONFIG_EMAC_BASE                     CONFIG_EMAC0_BASE
#define CONFIG_PHY_INTERFACE_MODE            SOCFPGA_PHYSEL_ENUM_MII

Device Tree Setup

Generate the device tree. EMAC0 is enabled in the device tree source, as shown below, and the I2C0 code source maintains its default settings.

aliases   {   
                  ethernet0 = "/soc/ethernet@ff700000";
          }; 
ethernet@ff700000 {
                     compatible = "altr,socfpga-stmmac","snps,dwmac-3.70a", "snps,dwmac";
                     reg = <0xff700000 0x2000>;
                     interrupts = <0x0 0x73 0x4>;
                     interrupt-names = "macirq";
                     mac-address = [00 00 00 00 00 00];
                     clocks = <0xd>;
                     clock-names = "stmmaceth";
                     status = "okay";
                     phy-mode = "mii";
                     phy-add r= <0xffffffff>;
                     snsp,
                  };

Board Setup and Booting Linux from the SD Card

Board setup is based on the GSRD Getting Started Guides.

Connect Ethernet Cable to the ENET1 Ethernet port.

Figure 8. Ethernet Connection on Cyclone^® V SoC Development Board
Slot in the SD card and power on the board.
Program the FPGA .sof file and perform a warm reset on the Cyclone^® V HPS component to reload the SD card image.
The kernel automatically enables and initializes EMAC0 then executes the dynamic host configuration protocol (DHCP) to obtain an IP address.
When the boot process has completed, login as root at the kernel terminal.

Figure 9. Kernel Login Example

Sample Application Example

The default kernel image contains many useful commands and built-in tools, such as ethtools and mii-tools. Some examples are illustrated in this section.

EMAC Test

Examples of commands that can be executed on EMAC0 are:

>udhcpc

Activate the dhcp server to request an IP address.

Figure 10. udhcpc Command Output

>ifconfig eth0

Initialize and enable or disable the network interface.

Figure 11. ifconfig eth0 Command Output

>ethtool eth0

Display and allow edits to the EMAC device parameters.

Figure 12. ethtool eth0 Command Output

I2C Test

The I²C interface can be tested using the following commands:

>i2cdetect -l

List the detected HPS I²C ports.

>i2cdetect -r 0

List the I²C slave devices connected to the HPS. "UU" is defined as device busy.

Figure 13. i2cdetect Command Outputs

>i2cset -y 0 0x66 0x10 0x55

I2C0 writes the data value 0x55 to the data address 0x10 of slave device at 0x66. The command is written in the order: device address, data address, data value.

>i2cget -y 0 0x66 0x10

Return data value at address 0x10 of the device slave at address 0x66.

Figure 14. i2cset and i2cget Commands

>i2cdump -y 0 0x66

Figure 15. i2cdump Command Output

Reference Documents

A summary list of the reference documents and sites mentioned in this application note follows:

AN 706 Revision History

Date	Version	Changes
May 2018	2018.05.07	SD/MMC can route signals to the FPGA Clarify that CAN is only supported by the Cyclone^® V SoC device family
July 2014	2014.07.17	Modified URLs of RocketBoards pages to version-specific links. Corrected AN 706 design example URL. Added steps to the Board Setup and Booting Linux from the SD Card section.
July 2014	2014.07.03	Initial Release