If a release note is not available for a specific IP core version, the IP
core has no changes in that version. Information on the latest update releases is in the
Altera Complete Design Suite Update Release Notes.
The Quartus II software v14.1 requires that you
specify a device if your IP core targets the Arria 10 device family. If you do
not specify your target Arria 10 device, the IP Upgrade tool insists that your
IP core requires upgrade, but does not clarify the reason.
You must ensure that you specify a device
for your v13.1 Arria 10 Edition or v14.0 Arria 10 Edition IP core variation and
regenerate it in the Quartus II software v14.1.
Enable phase compensation FIFO parameter.
xgmii_rx_inclk port, which is available when
Enable phase compensation FIFO is enabled.
pll_cal_busy_i port, which connects to the
pll_cal_busy output port of the external PLL.
Added a new Arria 10 SDC constraint
requirement. Refer to the "XAUI PHY TimeQuest SDC Constraint" section of the
Arria 10 Transceiver PHY User Guide.
Added support for Arria 10 devices. To use the
XAUI PHY IP core for Arria 10 devices, you must instantiate an external
transmit PLL. You can only use the ATX PLL IP core with the XAUI PHY IP core
for Arria 10 devices.
Enable dynamic reconfiguration parameter.
Removed the following parameters:
PMA control and configuration.
Added new port to enable connectivity with an
external transmit PLL and with the dynamic reconfiguration interface. Refer to
Arria 10 Transceiver PHY User Guide parameter and port
The XAUI PHY IP core does not support NCSIM
simulator. You will see an error message during elaboration.
The XAUI PHY IP core does not support VHDL. You
will get a compilation error when you simulate the XAUI PHY IP core generated
in VHDL. You must generate this IP core in Verilog.