I2S-TDM: 2S/TDM Multichannel Audio Transceiver
关于此报价
The I2S-TDM IP core is a highly configurable, full-duplex, multichannel serial audio transceiver. The transceiver can act as a controller (master) or a target (slave) for Inter-IC Sound (I2S) and Time-Division Multiplexed (TDM) audio interfaces, exchanging multi-channel audio samples over a configurable number of serial lines (pins).The I2S-TDM offers a number of configuration options to satisfy a wide range of serial audio interface requirements. The operation mode (controller or target), sample width, sample rate, frame format, number of channels and their allocation to physical lines are all programmable at run time. At synthesis time, designers can choose the maximum number of audio channels and serial data lines the transceiver can support. The core is designed for ease of use and integration and adheres to the industry’s best coding and verification practices. The core’s control and status registers (CSR) are accessed through a 32-bit AMBA® APB interface, or, optionally, an AXI4 Lite inter-face. The host system exchanges audio data with the core either via this CSR interface or via dedicated AXI4-Stream interfaces. The system interfaces operate with a clock that is independent from the audio master and serial bit clocks, and the core implements clean clock domain crossing boundaries.
技术规格
- 类别:
- 软件和 IP 核: FPGA 知识产权内核: 接口协议: 音频和视频
- 最终客户类型:
-
中小企业
企业
资源
采用的英特尔技术
英特尔® Stratix® 10 FPGA 和 SoC FPGA
英特尔® Cyclone® 10 FPGA
Cyclone® IV FPGA
Arria® V FPGA 和 SoC FPGA
英特尔® Arria® 10 FPGA 和 SoC FPGA
英特尔® Agilex™ 5 FPGA 和 SoC FPGA
Cyclone® V FPGA 和 SoC FPGA
英特尔® Agilex™ 7 FPGA 和 SoC FPGA
英特尔® Agilex™ 9 FPGA 和 SoC FPGA
Stratix® V FPGA
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I2s-tdm: 2s/tdm Multichannel Audio Transceiver
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