VESA® Display Stream Compression (DSC) 1.2b Decoder IP Core for Intel® FPGAs
VESA® Display Stream Compression (DSC) 1.2b Decoder IP Core for Intel® FPGAs
关于此报价
Key Features: VESA® Display Stream Compression (DSC) 1.2b compliant, supports all DSC 1.2b mandatory and optional encoding mechanisms, backward compatible to DSC v1.1. Configurable maximum display resolution up to 8K (FUHD) • 8, 10, 12 bits per video component, YCbCr and RGB video output format • 4:4:4, 4:2:2, and 4:2:0 native coding , resilient to bitstream corruption, 3 pixels / clock internal processing architecture in 4:4:4 • 6 pixels / clock internal processing architecture in 4:2:2 and 4:2:0. Parameterizable number of parallel slice decoder instances(1, 2, 4, 8) to adapt to the capability of the technology and target display resolutions used. Automatic run time configuration of the number of parallel slice decoder instances in use • Support for Intel® Arria®, Stratix®, and Agilex™ FPGAs • AXI-S (VPP-Lite) streaming interfaces for easy integration in the Intel® platform designer tool. Avalon memory-mapped interface for register access, PPS 128 bytes block decoding, Compliant solution for DisplayPort 1.4 or HDMI 2.1o compatibility for slices per line requirements. Supports flexible usage models and design architecture (inline decoding or panel frame buffer decoding).
详细信息
覆盖区域
亚太地区和日本:
东南亚
澳大利亚和新西兰
亚洲其他地区
韩国
中国台湾地区
南亚地区
日本
欧洲、中东和非洲:
中欧地区
独立国家联合体
中东、土耳其和非洲
西欧联盟地区
中东欧
北欧联盟地区
南欧联盟地区
中华人民共和国:
中华人民共和国
美洲:
拉美地区
北美地区
用例
传媒娱乐部 : 视频编辑和视觉效果 / 电影 / 电视
视频管理
互联工人
其它
数字标牌
工业
教育
汽车 : 车载信息娱乐
航空航天和国防
艺术和娱乐
其它
酒店和餐厅
游戏 : 电子竞技
游戏 : PC 游戏
技术规格
- 类别:
- 软件和 IP 核: FPGA 知识产权内核: 接口协议: 音频和视频
- 最终客户类型:
-
コンシューマー
中小規模のビジネス
エンタープライズ
その他
采用的英特尔技术
英特尔® Arria® 10 FPGA 和 SoC FPGA
英特尔® Agilex™ 7 FPGA 和 SoC FPGA
Arria® V FPGA 和 SoC FPGA
Stratix® FPGAs
Arria® FPGA
Stratix® IV FPGA
Stratix® II FPGA
英特尔® Stratix® 10 FPGA 和 SoC FPGA
Stratix® III FPGA
Arria® II FPGA
Stratix® V FPGA
资源
Rambus
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Rambus makes industry-leading chips and IP that advance data center connectivity and solve the bottleneck between memory and processing. The ongoing shift to the cloud, along with the widespread advancement of AI across data center, 5G, automotive and IoT, has led to an exponential growth in data usage and tremendous demands on data infrastructure. Creating fast and safe connections, both in and across systems, remains one of the most mission-critical design challenges limiting performance in advanced hardware. Rambus is ideally positioned to address this challenge as an industry pioneer with over 30 years of advanced semiconductor interconnect experience moving and protecting data. We are a leader in high-performance memory subsystems, providing chips, IP and innovations that maximize the performance and security in data-intensive systems. Whether in the cloud, at the edge or in your hand, real-time and immersive applications depend on data transfer speed and trust. Rambus products and innovations deliver the increased bandwidth, capacity and security required to usher in a new era of data center architectures and drive ever-greater end-user experiences.
Vesa® Display Stream Compression (dsc) 1.2b Decoder Ip Core For Intel® Fpgas
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