TCPIP-1G/10G: 1G/10G TCP/UDP/IP Hardware Stack
关于此报价
The TCPIP-1G/10G core implements a complete TCP/IP Hardware Protocol Stack. The core acts either as a server or a client and without any assistance from the host autonomously system, opens, maintains, and closes TCP connections. The system integrating the TCPIP-1G/10G core can configure network parameters and preferences by accessing its control registers, and the core is then able to receive and send data via streaming data interfaces. The core is highly configurable. The maximum number of simultaneous TCP sessions is configurable; it can be as high as 32,768 for devices like data servers, or as small as 1 for simpler edge devices. Further options include implementing a DHCP client, enabling or disabling the reassembly of out-of-order TCP packets data, and integrating a UDP hardware stack. Finally, users can choose the packet processing mode, either cut-through or store-and-forward. In cut-through mode, the payload data are delivered to the host system as they arrive without any internal packet buffering and before the packets’ integrity can be validated. As a result, the core operating in cut-through mode features extremely low latency and requires less memory, but it cannot reassemble out-of-order packets and may deliver data that will subsequently be marked as corrupted. Under the store-and-forward mode of operation, the core will always deliver verified, in-order packets but it will have higher latency and require more memory resources.
技术规格
- 类别:
- 软件和 IP 核: FPGA 知识产权内核: 接口协议: 以太网
- 最终客户类型:
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中小企业
企业
采用的英特尔技术
英特尔® Agilex™ 7 FPGA 和 SoC FPGA
Cyclone® V FPGA 和 SoC FPGA
英特尔® Stratix® 10 FPGA 和 SoC FPGA
Stratix® V FPGA
Arria® V FPGA 和 SoC FPGA
英特尔® Agilex™ 5 FPGA 和 SoC FPGA
英特尔® Cyclone® 10 FPGA
英特尔® Agilex™ 9 FPGA 和 SoC FPGA
英特尔® Arria® 10 FPGA 和 SoC FPGA
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Tcpip-1g/10g: 1g/10g Tcp/udp/ip Hardware Stack
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