LIN: LIN Bus Master/Slave Controller
关于此报价
The LIN core is a communication controller that transmits and receives complete LIN frames to perform serial communication according to the LIN Protocol Specification. The LIN controller can be implemented as a master or as a slave and operate on LIN 1.3, 2.0, 2.1 or 2.2 LIN network. It uses a single master/multiple slave concept for message transfer between nodes of the LIN network. The message transfer can be controlled via a microcontroller interface and a LIN transceiver is needed for the connection to the LIN bus. The LIN core is available in two versions: Standard and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The Safety-Enhanced versions are certified as ISO- 26262 ASIL-D Ready. The robustly verified core has been production-proven multiple times.
技术规格
- 类别:
- 软件和 IP 核: FPGA 知识产权内核: 接口协议: 通信
- 最终客户类型:
-
中小企业
其它
企业
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英特尔® Stratix® 10 FPGA 和 SoC FPGA
Cyclone® IV FPGA
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英特尔® Agilex™ 7 FPGA 和 SoC FPGA
Stratix® IV FPGA
英特尔® Arria® 10 FPGA 和 SoC FPGA
Stratix® V FPGA
英特尔® Cyclone® 10 FPGA
Cyclone® V FPGA 和 SoC FPGA
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Lin: Lin Bus Master/slave Controller
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