JPEG-EX-S: Baseline and Extended JPEG Encoder
关于此报价
This IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-performance, hardware JPEG encoder with very low processing latency. The JPEG-EX-S Encoder produces compressed JPEG images and the video payload for Motion-JPEG container formats. It accepts images with 8- or 12-bit color samples and up to four color components, in all widely-used color subsampling formats. The encoder processes one color sample per clock cycle, enabling it to compress multiple Full-HD channels even in low-cost FPGAs. One of the smallest JPEG encoders available, it synthesizes to about 4,000 ALMs. The core operates without any assistance from the host processors, and uses AXI-stream interfaces for pixel and stream data, and a 32-bit APB slave interface for registers access. FEATURES: Performs Baseline and Extended Sequential DCT JPEG encoding of images or video for ASICs or FPGAs, with small silicon area, high performance, and low latency. Standards Support ISO/IEC 10918-1 Standard Baseline and Extended Sequential DCT modes Single-frame JPEG images and Motion JPEG payloads 8-bit and 12-bit per color samples Up to four color components; any image size up to 64k x 64k All scan configurations and all JPEG formats APP, COM, and restart markers Programmable Huffman and Quantization tables Rate Control Options Image: Limits the size of each individual frame Video: Regulates bit rate over a number of input frames. Interfaces AXI Streaming I/O data interfaces APB Control/Status interface Performance and Size One encoded sample per clock cycle Small silicon footprint (about 80k ASIC gates) Ease of Integration Automatic program-once/encode-many operation Simple, dedicated timestamps interface Included bit-accurate software model generates test vectors, expected results, and core programming values Optional Raster-to-Block Conversion with AXI or standard memory interface to the lines buffer
技术规格
- 类别:
- 软件和 IP 核: FPGA 知识产权内核: DSP: 视频和图像处理
- 最终客户类型:
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Jpeg-ex-s: Baseline And Extended Jpeg Encoder
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