仅对英特尔可见 — GUID: mhy1565140573848
Ixiasoft
4.1. Intel® Agilex™ 高速SERDES I/O概述
4.2. 使用LVDS SERDES Intel FPGA IP实现高速LVDS I/O
4.3. Intel® Agilex™ LVDS SERDES发送器
4.4. Intel® Agilex™ LVDS SERDES接收器
4.5. LVDS SERDES IP初始化和复位
4.6. External PLL模式的 Intel® Agilex™ LVDS接口
4.7. Intel® Agilex™ LVDS SERDES源同步时序预算
4.8. LVDS SERDES IP时序
4.9. LVDS SERDES IP设计实例
仅对英特尔可见 — GUID: mhy1565140573848
Ixiasoft
2.3.1. 在 Intel® Quartus® Prime软件中配置I/O Assignment
下表列出了可在assignment editor和pin planner中使用的可编程IOE设置的assignment名称。
功能 | Intel® Quartus® Prime Assignment名称 |
值 |
条件 |
---|---|---|---|
摆率控制 | Slew Rate | 0 (Slow), 1 (Medium), 2(Fast). Default is 2. | |
I/O延迟 | Input Delay Chain Setting Output Delay Chain Setting |
Refer to the device data sheet | — |
开漏输出 | Auto Open-Drain Pins | On, Off. Default is Off | — |
总线保持 | Enable Bus-Hold Circuitry | On, Off. Default is Off. | 如果使用弱上拉电阻功能则禁用。 |
弱上拉电阻 | Weak Pull-Up Resistor | On, Off. Default is Off. | 如果使用总线保持功能则禁用。 |
预加重 | Programmable Pre-emphasis | 0 (Off), 1 (Low Power), 2 (Const Z). Default is 1. | — |
De-emphasis | Programmable De-emphasis | High, High Const Z, Low, Low Const Z, Medium, Medium Const Z, OFF. Default is OFF. | — |
差分输出电压 | Programmable Differential Output Voltage (VOD) | 0 (low), 1 (medium low), 2 (medium high), 3 (high). Default is 2. | — |