仅对英特尔可见 — GUID: jdr1489992896494
Ixiasoft
1. Intel® Cyclone® 10 GX器件中的逻辑阵列模块与自适应逻辑模块
2. Intel® Cyclone® 10 GX器件中的嵌入式存储器模块
3. Intel® Cyclone® 10 GX器件中的精度可调DSP模块
4. Intel® Cyclone® 10 GX器件中的时钟网络和PLL
5. Intel® Cyclone® 10 GX 器件的I/O和高速I/O
6. Intel® Cyclone® 10 GX 器件的外部存储器接口
7. Intel® Cyclone® 10 GX器件中的配置,设计安全和远程系统更新
8. Intel® Cyclone® 10 GX器件的SEU缓解
9. Intel® Cyclone® 10 GX器件中的JTAG边界扫描测试
10. Intel® Cyclone® 10 GX器件中的电源管理
5.1. Intel® Cyclone® 10 GX 器件中的I/O和差分I/O缓冲
5.2. Intel® Cyclone® 10 GX器件中的I/O标准和电压电平
5.3. Intel® Cyclone® 10 GX 器件的Intel FPGA I/O IP内核
5.4. Intel® Cyclone® 10 GX 器件的I/O资源
5.5. Intel® Cyclone® 10 GX 器件的体系结构和I/O的一般功能
5.6. Intel® Cyclone® 10 GX 器件的高速源同步SERDES和DPA
5.7. 在 Intel® Cyclone® 10 GX 器件中使用I/O和高速I/O
5.8. Intel® Cyclone® 10 GX器件的I/O和高速I/O的修订历史
6.1. Intel® Cyclone® 10 GX 外部存储器接口关键功能特性的解决方案
6.2. Intel® Cyclone® 10 GX器件支持的存储器标准
6.3. Intel® Cyclone® 10 GX 器件中的外部存储器接口宽度
6.4. Intel® Cyclone® 10 GX 器件中的外部存储器接口I/O管脚
6.5. Intel® Cyclone® 10 GX 器件封装中支持的存储器接口
6.6. Intel® Cyclone® 10 GX 器件中的外部存储器接口IP支持
6.7. Intel® Cyclone® 10 GX 器件的外部存储器接口体系结构
6.8. Intel® Cyclone® 10 GX器件中的外部存储器接口修订历史
仅对英特尔可见 — GUID: jdr1489992896494
Ixiasoft
9.1.2. Supported JTAG Instruction
JTAG Instruction | Instruction Code | Description |
---|---|---|
SAMPLE 25 / PRELOAD | 00 0000 0101 |
|
EXTEST | 00 0000 1111 |
|
BYPASS | 11 1111 1111 |
|
USERCODE | 00 0000 0111 | Selects the 32-bit USERCODE register and places it between the TDI and TDO pins to allow serial shifting of USERCODE out of TDO. |
IDCODE | 00 0000 0110 |
|
HIGHZ | 00 0000 1011 |
|
CLAMP | 00 0000 1010 |
|
PULSE_NCONFIG | 00 0000 0001 | Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is not affected. |
EXTEST_PULSE | 00 1000 1111 | Enables board-level connectivity checking between the transmitters and receivers that are AC coupled by generating three output transitions:
|
EXTEST_TRAIN | 00 0100 1111 | Behaves the same as the EXTEST_PULSE instruction except that the output continues to toggle on the TCK falling edge as long as the TAP controller is in the RUN_TEST/IDLE state. |
SHIFT_EDERROR_REG | 00 0001 0111 | The JTAG instruction connects the EMR to the JTAG pin in the error detection block between the TDI and TDO pins. |
注: If the device is in a reset state and the nCONFIG or nSTATUS signal is low, the device IDCODE might not be read correctly. To read the device IDCODE correctly, you must issue the IDCODE JTAG instruction only when the nCONFIG and nSTATUS signals are high.
25 The SAMPLE JTAG instruction is not supported for high-speed serial interface (HSSI) pins.