仅对英特尔可见 — GUID: nik1398706959728
Ixiasoft
2.7.1. PIPE的收发器通道数据通路
2.7.2. 所支持的PIPE特性
2.7.3. 如何连接PIPE Gen1、Gen2和Gen3模式的TX PLL
2.7.4. 如何在Arria 10收发器中实现PCI Express* (PIPE)
2.7.5. PIPE的Native PHY IP参数设置
2.7.6. PIPE的fPLL IP参数内核设置
2.7.7. PIPE的ATX PLL IP参数内核设置
2.7.8. PIPE的Native PHY IP端口
2.7.9. PIPE的fPLL端口
2.7.10. PIPE的ATX PLL端口
2.7.11. 到TX去加重的预置映射
2.7.12. 如何对PIPE配置布局通道
2.7.13. Gen3数据速率的PHY IP Core for PCIe* (PIPE)链路均衡
2.7.14. 使用收发器套件(TTK)/系统控制台/重配置接口进行手动调节 Arria® 10 PCIe设计(Hard IP(HIP)和PIPE) (仅用于调试)
2.9.1.1. 如何在Arria 10收发器中实现Basic (Enhanced PCS)和Basic with KR FEC收发器配置规则
2.9.1.2. Basic (Enhanced PCS)和Basic with KR FEC的Native PHY IP参数设置
2.9.1.3. 如何在Basic Enhanced PCS中低延时
2.9.1.4. Enhanced PCS FIFO操作
2.9.1.5. TX Data Bitslip(TX数据比特滑移)
2.9.1.6. TX数据极性反转
2.9.1.7. RX Data Bitslip(RX数据比特滑移)
2.9.1.8. RX数据极性反转
2.9.2.1. 字对齐器手动模式
2.9.2.2. 字对齐器同步状态机模式
2.9.2.3. RX比特滑移
2.9.2.4. RX极性反转
2.9.2.5. RX比特反转
2.9.2.6. RX字节反转
2.9.2.7. 基本(单宽度)模式下的速率匹配FIFO
2.9.2.8. 速率匹配FIFO基本(双宽度)模式
2.9.2.9. 8B/10B编码器和解码器
2.9.2.10. 8B/10B TX差异控制
2.9.2.11. 如何在基本模式下使能低延时
2.9.2.12. TX比特滑移
2.9.2.13. TX极性倒转
2.9.2.14. TX比特反转
2.9.2.15. TX字节反转
2.9.2.16. 如何在 Arria® 10 收发器中实现Basic,Basic with Rate Match收发器配置规则
2.9.2.17. Basic,Basic with Rate Match配置的Native PHY IP参数设置
6.1. 重新配置通道和 PLL 模块
6.2. 与重配置接口进行交互
6.3. 配置文件
6.4. 多种重配置设置档
6.5. 嵌入重配置流光器
6.6. 仲裁
6.7. 动态重配置的建议
6.8. 执行动态重配置的步骤
6.9. 直接重配置流程
6.10. Native PHY IP或PLL IP内核指导的重配置流程
6.11. 特殊情况的重配置流程
6.12. 更改 PMA 模拟参数
6.13. 端口和参数
6.14. 在多个IP模块之中动态重配置接口合并
6.15. 嵌入式调试功能
6.16. 使用数据码型生成器和检查器
6.17. 时序收敛建议
6.18. 不支持的功能
6.19. Arria® 10 收发器寄存器映射
8.7.1. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T
8.7.2. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T
8.7.3. XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP
8.7.4. XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP
8.7.5. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
8.7.6. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
8.7.7. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
8.7.8. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
仅对英特尔可见 — GUID: nik1398706959728
Ixiasoft
2.8.5. CPRI的Native PHY IP参数设置
参数 | 值 |
---|---|
Message level for rule violations | error warning |
Transceiver configuration rules | CPRI (Auto) CPRI (Manual) |
PMA configuration rules | basic |
Transceiver mode | TX/RX Duplex |
Number of data channels | 1-36 |
Data rate | 1228.8 Mbps 2457.6 Mbps 3072 Mbps 4915.2 Mbps 6144 Mbps 8110.08 Mbps 9830.4 Mbps 10137.6 Mbps 45 12165.12 Mbps 45 |
Enable datapath and interface reconfiguration | Off |
Enable simplified data interface | On |
参数 | 值 |
---|---|
TX channel bonding mode | Not Bonded / PMA Bonding Only / PMA and PCS Bonding |
TX local clock division factor | 1 |
Number of TX PLL clock inputs per channel | 1 |
Initial TX PLL clock input selection | 0 |
Enable tx_pma_clkout port | Off |
Enable tx_pma_div_clkout port | On |
tx_pma_div_clkout division factor | 2 |
Enable tx_pma_elecidle port | Off |
Enable tx_pma_qpipullup port (QPI) | Off |
Enable tx_pma_qpipulldn port (QPI) | Off |
Enable tx_pma_txdetectrx port (QPI) | Off |
Enable tx_pma_rxfound port (QPI) | Off |
Enable rx_seriallpbken port | Off |
参数 | 值 |
---|---|
Number of CDR reference clocks | 1 |
Selected CDR reference clock | 0 |
Selected CDR reference clock frequency | 选择由Quartus Prime定义的合法范围 |
PPM detector threshold | 1000 |
CTLE adaptation mode | manual |
DFE adaptation mode | disabled |
Number of fixed dfe taps | 3 |
Enable rx_pma_clkout port | Off |
Enable rx_pma_div_clkout port | On |
rx_pma_div_clkout division factor | 2 |
Enable rx_pma_clkslip port | Off |
Enable rx_pma_qpipulldn port (QPI) | Off |
Enable rx_is_lockedtodata port | On |
Enable rx_is_lockedtoref port | On |
Enable rx_set_locktodata and rx_set_locktoref ports | Off |
Enable rx_seriallpbken port | Off |
Enable PRBS verifier control and status ports | Off |
参数 | 值 |
---|---|
Standard PCS / PMA interface width | 20 |
FPGA fabric / Standard TX PCS interface width | 32 |
FPGA fabric / Standard RX PCS interface width | 32 |
Enable 'Standard PCS' low latency mode | Off |
TX FIFO mode | register_fifo |
RX FIFO mode | register_fifo |
Enable tx_std_pcfifo_full port | Off |
Enable tx_std_pcfifo_empty port | Off |
Enable rx_std_pcfifo_full port | Off |
Enable rx_std_pcfifo_empty port | Off |
TX byte serializer mode | Serialize x2 |
RX byte deserializer mode | Deserialize x2 |
Enable TX 8B/10B encoder | On |
Enable TX 8B/10B disparity control | Off |
Enable RX 8B/10B decoder | On |
RX rate match FIFO mode | Disabled |
RX rate match insert / delete -ve pattern (hex) | 0x00000000 |
RX rate match insert / delete +ve pattern (hex) | 0x00000000 |
Enable rx_std_rmfifo_full port | Off |
Enable rx_std_rmfifo_empty port | Off |
PCI Express* Gen3 rate match FIFO mode | Bypass |
Enable TX bit slip | Off (CPRI自动配置) On (CPRI手动配置) |
Enable tx_std_bitslipboundarysel port | Off (CPRI自动配置) On (CPRI手动配置) |
RX word aligner mode | deterministic latency (CPRI自动配置) manual (FPGA fabric controlled) (CPRI手动配置) |
RX word aligner pattern length | 10 |
RX word aligner pattern (hex) | 0x000000000000017c |
Number of word alignment patterns to achieve sync | 3 46 |
Number of invalid data words to lose sync | 3 46 |
Number of valid data words to decrement error count | 3 46 |
Enable fast sync status reporting for deterministic latency SM | On / Off |
Enable rx_std_wa_patternalign port | On / Off |
Enable rx_std_wa_a1a2size port | Off |
Enable rx_std_bitslipboundarysel port | Off (CPRI自动配置) On (CPRI手动配置) |
Enable rx_bitslip port | Off (CPRI自动配置) On (CPRI手动配置) |
Bit Reversal and Polarity Inversion下的所有选项 | Off |
PCIe* Ports下的所有选项 | Off |
参数 | 值 |
---|---|
Enable dynamic reconfiguration | Off |
Share reconfiguration interface | Off |
Enable Altera Debug Master Endpoint | Off |
Enable embedded debug | Off |
Enable capability registers | Off |
Set user-defined IP identifier | 0 |
Enable control and status registers | Off |
Enable prbs soft accumulators | Off |
Configuration file prefix | altera_xcvr_native_a10 |
Generate SystemVerilog package file | Off |
Generate C header file | Off |
Generate MIF (Memory Initialization File) | Off |
参数 | 值 |
---|---|
Generate parameter documentation file | On |
45 10137.6 Mbps和12165.12 Mbps是通过选择Transceiver configuration rules下的10GBase-R或10GBase-R 1588来实现的。当CPRI数据速率是10137.6 Mbps或更高时选择Enhanced PCS。
46 当收发器PHY处于CPRI模式时,不使用这些参数和值。