Intel® Quartus® Prime Standard Edition用户指南: 调试工具

ID 683552
日期 9/24/2018
Public
文档目录

3.3.2.1. 误码率测试配置( Stratix® V)

使用以下配置在 Stratix® V设计中执行误码率测试。
误码率测试配置( Stratix® V)


系统连接:误码率测试
From To
Your Design Logic Data Pattern Generator bypass port
Data Pattern Generator PHY input port
JTAG to Avalon® Master Bridge Intel FPGA Avalon® Data Pattern Generator

JTAG to Avalon® Master Bridge

Intel FPGA Avalon® Data Pattern Checker

JTAG to Avalon® Master Bridge PHY input port
Data Pattern Checker PHY output port
Transceiver Reconfiguration Controller PHY input port