双倍数据速率I/O (ALTDDIO_IN、ALTDDIO_OUT和ALTDDIO_BIDIR) IP内核用户指南

ID 683148
日期 1/23/2015
Public

1.6.1.1. 创建ALTDDIO_BIDIR模块

按照以下步骤创建ALTDDIO_BIDIR模块:
  1. ALTDDIO_DesignExample_ex2.zip文件解压缩到PC上的任何工作目录中。
  2. 在Quartus II软件中,打开ex2.qar 过程。
  3. 在Tools菜单中,选择MegaWizard Plug-In Manager
  4. 在MegaWizard插件管理器对话框中,选择Create a new custom megafunction variation,并点击NextMegaWizard Plug-In Manager 页面显示。
  5. 在MegaWizard插件管理器页面,选择或验证该表中所示的配置设置。点击Next,从而进入下一个页面。
    参数编辑器页面 参数
    2a Which megafunction would you like to customize I/O文件夹中,选择ALTDDIO_BIDIR
    Which device family will you be using? Stratix
    Which type of output file do you want to create? VHDL
    What name do you want for the output file? alt_bid
    Return to this page for another create operation Turned off
    3 Currently selected device family Stratix IV
    Match project/default Turned on
    Width: (bits) 8
    Use ‘aclr’ port Turned off
    Use ‘aset’ port Turned off
    Not used Turned on
    Registers power up high Turned off
    Use ‘sclr’ port Turned off
    Use ‘sset’ port Turned off
    Not used Turned on
    Invert ‘padio’ port Turned off
    4 Use ‘inclocken’ and ‘outclocken’ ports Turned off
    Use output enable port Turned on
    Use ‘oe_out’ port to connect to tri-state output buffer(s) Turned off
    Register ‘oe’ port Turned off
    Delay switch-on by half a clock cycle Turned off
    Use ‘combout’ port Turned off
    Use ‘dqsundelayedout’ port Turned off
    Use ‘dataout_h’ and ‘dataout_l” ports Turned on
    Implement input registers in LEs Turned off
    5 Generate netlist Turned off
    6 Variation file Turned on
    Quartus II IP file Turned on
    Quartus II symbol file (.bsf) Turned off
    Instantiation template file Turned on
    Verilog HDL black box file (_bb.v) Turned on
    AHDL Include file (.inc) Turned off
    VHDL component declaration file (.cmp) Turned on
    PinPlanner ports file (.PPF) Turned on
  6. 点击Finish

    构建了ALTDDIO_BIDIR模块。