Develop for the Next Generation of RISC-V* Processors with SYCL*

An increasing number of companies are adopting RISC-V* processors. This coincides with a demand from software developers for processors that can help deploy AI and high-performance computing (HPC) applications. How can software developers be enabled to take advantage of the latest RISC-V processors, especially those designed for AI processing? One crucial method is using a programming model that can achieve portability across RISC-V processors. SYCL* (a programming language) is quickly bringing this solution.

This panel session explored:

  • The latest developments from companies involved in bringing the latest RISC-V processors to market
  • The needs of researchers and developers writing the next generation of AI and HPC software


Raja Appuswamy is an assistant professor in the data science department at EURECOM (a graduate school located in southern France). He was a researcher and visiting professor at École Polytechnique Fédérale de Lausanne (EPFL), a visiting researcher in the Systems and Networking group at Microsoft* Research, and a software development engineer in the Windows* 7 kernel team at Microsoft.

Michael Wong is an engineer at Codeplay* Software, a Scottish company that produces compilers, debuggers, runtimes, testing systems, and other specialized tools to aid software development. He is a member of the Khronos* Group, Motor Industry Software Reliability Association (MISRA), and Automotive Open System Architecture (AUTOSAR*), and is chair of the Khronos Group C++ heterogeneous programming language, SYCL. For twenty years, he was the senior technical strategy architect for IBM* compilers.

Hideki Sugimoto has over 25 years of experience at NEC Corporation as a processor architect, and as an IP, MCU, system-on-a-chip (SoC) designer. He is currently chief technology officer of NSITEXE, Inc. and is working to innovate embedded SoC architecture to make it more generic, flexible, and scalable.

Dr. Zdenek Přikryl played a major role in the research at Brno University of Technology that enabled the creation of processor development tools at Codasip*. He developed a methodology that is based on automatically generating hardware and software development kits from a processor description language. Zdenek has been the chief architect of Codasip Studio for over ten years. He was also the architect of diverse processor cores including 16-bit and 32-bit architectures for IoT, 32-bit and 64-bit digital signal processor (DSP) oriented architectures, and architectures that are capable for Linux*. All of these architectures were developed using Codasip Studio and many were based on the RISC-V ISA processor.

Mark Himelstein is currently at RISC-V. He was the president of Heavenstone, Inc., which concentrated on strategic, management, and technology consulting for providing hardware and software product architecture, analysis, mentoring, and interim management. Mark has a bachelor's degree in computer science and math from Wilkes University in Pennsylvania and a master's degree in computer science from University of California Davis. In addition to publishing numerous technical papers and holding many patents, he is the author of 100 Questions to Ask Your Software Organization.