Generation Report - DDR SDRAM Controller v9.0

Entity Nameddr_sdram_0_auk_ddr_sdram
Variation Nameddr_sdram_0
Variation HDLVHDL
Output Directory/net/sj-itnas01b/vol/vol1/abg/home/home/users/holiu/Ethernet_Project/90/May20_32k32k_timing/May7_startfromFeb22_Working90Tse

File Summary

The MegaWizard interface is creating the following files in the output directory:
FileDescription
ddr_sdram_0.vhdA MegaCore® function variation file, which defines a VHDL top-level description of the custom MegaCore function. Instantiate the entity defined by this file inside of your design. Include this file when compiling your design in the Quartus II software.
ddr_sdram_0.cmpA VHDL component declaration for the MegaCore function variation. Add the contents of this file to any VHDL architecture that instantiates the MegaCore function.
ddr_sdram_0_auk_ddr_dqs_group.vhdDesign file containing the datapath byte groups.
ddr_sdram_0_auk_ddr_clk_gen.vhdDesign file containing the clock output generators.
ddr_sdram_0_auk_ddr_datapath.vhdDesign file that instantiates the byte groups and the clock output generators.
ddr_sdram_0_auk_ddr_sdram.vhdDesign file that instantiates the controller logic and the datapath.
ddr_sdram_0_auk_ddr_dll.vhdDesign file containing the Stratix or Stratix II DLL.
ddr_sdram_0_debug_design.vhd Example top-level design file.
testbench | ddr_sdram_0_debug_design_tb.vhdTestbench for the example top level design file.
add_constraints_for_ddr_sdram_0.tclDDR constraints script.
verify_timing_for_ddr_sdram_0.tclPost-compilation timing analysis script.
constraints_out.txtLog file that IP Toolbench creates while generating the add constraints script.
ddr_sdram_0_ddr_settings.txtCritical settings file that stores the custom variation’s parameters. IP Toolbench uses this file to generate the add constraints script. The verify timing script and the DDR Timing Wizard also read this file.
ddr_sdram_0_pre_compile_ddr_timing_summary.txtLog file that stores the results of the precompilation system timing analysis.
ddr_sdram_0.qipContains Quartus II project information for your MegaCore function variation.
ddr_sdram_0.htmlThe MegaCore function report file.

MegaCore Function Variation File Ports

NameDirectionWidth
write_clkINPUT1
clkINPUT1
clkINPUT1
reset_nINPUT1
write_clkINPUT1
local_read_reqINPUT1
local_write_reqINPUT1
local_addrINPUT23
local_wdataINPUT32
local_beINPUT4
local_readyOUTPUT1
local_rdataOUTPUT32
local_rdata_validOUTPUT1
clk_to_sdramOUTPUT1
clk_to_sdram_nOUTPUT1
ddr_cs_nOUTPUT1
ddr_ckeOUTPUT1
ddr_aOUTPUT13
ddr_baOUTPUT2
ddr_ras_nOUTPUT1
ddr_cas_nOUTPUT1
ddr_we_nOUTPUT1
ddr_dqBIDIR16
ddr_dqsBIDIR2
ddr_dmOUTPUT2
dqs_delay_ctrlINPUT6
stratix_dll_controlOUTPUT1
dqsupdateINPUT1