AN 686: Implementing 9.8 Gbps CPRI in Arria V GT and ST Devices

ID 683613
Date 12/06/2013
Public

1. Implementing 9.8G CPRI in Arria V GT and ST FPGAs

This application note describes the implementation of 9.8304 Gbps Common Public Radio Interface (CPRI) using the Arria® V GT and Arria® V ST FPGA transceivers.

The hard physical coding sublayer (PCS) block in Arria V FPGAs supports data rates up to 6.5536 Gbps. To implement 9.8304 Gbps CPRI, the transceiver is configured in Physical Media Attachment (PMA) direct mode and a soft PCS block is implemented in the FPGA core.

The following sections describe the configuration of Native PHY IP in PMA direct mode, the architecture of the soft PCS in the FPGA core, and the steps for auto rate negotiation from 9.8304 Gbps down to 1.2288 Gbps.

Note: This application note is accompanied by a reference design to demonstrate the soft PCS implementation and auto rate negotiation from 9.8304 Gbps down to 1.2288 Gbps.