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Advanced Metal Gate/High-K Dielectric Stacks for CMOS TransistorsWe have successfully engineered n-type and p-type metal electrodes with the correct work functions on high-K gate dielectrics for high-performance CMOS applications. The resulting metal gate/high-K dielectric stacks have equivalent oxide thickness (EOT) of 1.0nm with negligible gate oxide leakage, desirable transistor threshold voltages for n- and p-channel MOSFETs, and transistor channel mobilities close to those of SiO2. The CMOS transistors fabricated with these advanced metal gate/high-K dielectric stacks achieve the expected high drive current performance.IntroductionFor more than 15 years the physical thickness of SiO2 has been aggressively scaled for low-power, high-performance CMOS applications. Figure 1 shows the physical thickness trend of SiO2. Recently SiO2 with physical thickness of 1.2nm (see Fig. 2) has been successfully implemented in the 90nm logic node . In addition, SiO2 with physical thickness of 0.8nm (see Fig. 3) has been demonstrated in the laboratory [2-3]. Continual gate oxide scaling, however, will require the use of dielectric materials with higher dielectric constant (K) since i) the gate oxide leakage is increasing with decreasing SiO2 thickness, and ii) SiO2 is running out of atoms for further scaling. So far the most common high-K dielectric materials investigated by both academia and industry are Hf-based and Zr-based [4-5].Read the full Advanced Metal Gate/High-K Dielectric Stacks for CMOS Transistors Paper.
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Jasper Forest 简介： 英特尔® 至强™ 处理器家族的最新特性。