英特尔® 至强™ 处理器 5600 系列数据表,第 2 卷

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Intel® Xeon® Processor 5600 Series Datasheet, Vol. 2

This document provides Intel® Xeon® processor 5600 series content, and is intended to supplement the functional descriptions and register documentation found in the Intel® Xeon® Processor 5500 Series Datasheet, Volume 2.

The Intel® Xeon® processor 5600 series is the next generation DP server/workstation processor based on the Intel® Xeon® Processor 5500 Series architecture, and utilizing 32 nm process technology. The Intel Xeon processor 5600 series upgrades Intel® 5500 platforms, and provides the following new features and capabilities:
• Up to 6-core operation (up to 12 threads per socket with Intel® Hyper-Threading Technology)
• 12 MB of shared Last-Level Cache

<• Support for DDR3L (1.35 V) DIMMs
• Platform security capabilities using Intel® Trusted Execution Technology (Intel® TXT)
• Support for hardware-based 2x memory refresh via DDR_THERM2# pin
• Advanced Encryption Standard - New Instructions (AES-NI)
• Memory sparing support

Register Description

The processor supports PCI configuration space accesses using the mechanism denoted as Configuration Mechanism in the PCI specification as defined in the PCI Local Bus Specification, as well as the PCI Express* enhanced configuration mechanism as specified in the PCI Express Base Specification. All the registers are organized by bus, device, function, and so on as defined in the PCI Express Base Specification. All processor registers appear on the PCI bus assigned for the processor socket. Bus number is derived by the max bus range setting and processor socket number. All multi-byte numeric fields use “little-endian” ordering (that is, lower addresses contain the least significant parts of the field).

Read the full Intel® Xeon® Processor 5600 Series Datasheet, Vol. 2.