Intel® Silicon View Technology (Intel® SVT)
Accelerating Intel® architecture-based platform debug, electrical validation, and board-manufacturing testing
4th Generation Intel® Core™ Processor Capabilities
Software tracing: 4th generation Intel® Core™ processors support Architectural Event Trace (AET) capability to augment debuggers by showing a trace of events that occurred during software execution. AET is enabled by setting bits in a model-specific register (MSR), thereby instrumenting monitoring of software execution without directly modifying the software itself. This results in generated Intel® architecture state information (data) for architecture events as they are encountered during execution.
Examples of architectural events are interrupts, exceptions, read from model-specific register (RDMSR), write to model-specific register (WRMSR), IN/OUT instructions, code/data breakpoints, system management interrupt (SMI), and MWAIT. State information may be obtained directly over a debug port in real time or stored in memory, time-stamped, and further processed by debug tools to analyze software execution. During platform debug, software debuggers can also be set up to trigger and halt on failing conditions.
Hardware tracing: 4th generation Intel Core processors support capabilities to observe key internal buses and nodes that are useful for both hardware and software developers. While software is executing on the processor, transactions and events inside the CPU can be traced in real time to aid the debug of system failures. While transactions traced may vary from product to product due to differences in microarchitecture, information is provided about memory, I/O traffic, events requested by software, core ID, special cycles, and cache coherency attributes. This helps debug common use cases such as system hangs, I/O failures and platform interaction, data corruption, power issues, and more.
Debug ports: In addition to the debug ports, such as joint test action group (JTAG), top-side probe, and others that are supported in prior generations of the Intel Core processor family, Intel® Silicon View Technology (Intel® SVT) in 4th generation platforms introduces the Direct Connect Interface (DCI) feature. The goal of DCI capability is to reuse standard I/O ports as debug ports. USB 3.0, supported on Ultrabook™ platforms, is the first such supported capability. This enables closed chassis test and debug, which is especially helpful for thermally sensitive small form factor 4th generation Intel Core processor–based platforms such as Ultrabook™. The target system and host systems are connected via USB 3.0—either directly or via the Intel® closed chassis adapter (CCA).
Intel SVT supports electrical validation of CPU interfaces, including PCIe* graphics, Direct Media Interface (DMI), and double data rate (DDR), and platform controller hub (PCH) interfaces, including SATA, USB, DMI, and PCIe, on 4th generation Intel Core–based platforms. These capabilities span across both functional and synthetic mode testing with stressful pseudorandom pattern generation. Features include timing and voltage margining, bit error ratio (BER) tests, and full eye margin, as well as equalization and transmitter swing control. These capabilities are complemented with powerful reporting, visualization, and analytical features such as validation methodology and eye mask guidance.
Board Manufacturing Testing
Intel SVT helps test CPU and PCH interfaces on 4th generation Intel Core–based platforms. Test patterns are written and read at speed, independent of an operating system running on the target. These patterns are diagnosed for defects. Test tools are available to sequence power, test clocks, and margin interfaces to increase defect coverage.
Contact your Intel representative to learn how you can get access to these technologies under non-disclosure agreement (NDA).