PCI Express* Provides Reliability, Availability, and Serviceability
White Paper
The components of PCI Express RAS
PCI Express is rich in RAS capabilities, which are vital to customers in corporate IT and the data center. This means that by incorporating PCI Express RAS into their early product designs, platform OEMs and adapter developers can position themselves well ahead of their competition. Moreover, they can do so without having to make changes in operating systems or drivers because PCI Express defines an evolutionary bus model that is fully compatible with existing software infrastructures. Software developers also can position themselves ahead of the competition by taking advantage of the advanced RAS features of PCI Express adapters and promoting those features into standard usage models. PCI Express RAS consists of three fundamental components: (1) a reliable protocol architecture; (2) device-level protocol error detection, correction, and reporting; and (3) device level requirements for support of a hot-plug usage model (SHPC 1.0) based on current industry standards.
Reliable protocol architecture
To enable the smooth implementation of RAS, PCI Express provides reliable protocol error detection, correction, and reporting capabilities at three cooperative functional layers of a device architecture: physical, data link, and transaction. In addition, PCI Express defines the base unit of interdevice bus communication as the transaction layer packet (TLP). Within a PCI Express–based design, one or more TLPs combine to form a transaction, which is transmitted over a link from one device on the bus to another. For a given TLP, a device provides device-level error detection and correction through analysis of reliability mechanisms present in every TLP. These error detection/correction responsibilities span the three functional device layers.
Read the full PCI Express* White Paper.
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PCI Express* Provides Reliability, Availability, and Serviceability
White Paper
The components of PCI Express RAS
PCI Express is rich in RAS capabilities, which are vital to customers in corporate IT and the data center. This means that by incorporating PCI Express RAS into their early product designs, platform OEMs and adapter developers can position themselves well ahead of their competition. Moreover, they can do so without having to make changes in operating systems or drivers because PCI Express defines an evolutionary bus model that is fully compatible with existing software infrastructures. Software developers also can position themselves ahead of the competition by taking advantage of the advanced RAS features of PCI Express adapters and promoting those features into standard usage models. PCI Express RAS consists of three fundamental components: (1) a reliable protocol architecture; (2) device-level protocol error detection, correction, and reporting; and (3) device level requirements for support of a hot-plug usage model (SHPC 1.0) based on current industry standards.
Reliable protocol architecture
To enable the smooth implementation of RAS, PCI Express provides reliable protocol error detection, correction, and reporting capabilities at three cooperative functional layers of a device architecture: physical, data link, and transaction. In addition, PCI Express defines the base unit of interdevice bus communication as the transaction layer packet (TLP). Within a PCI Express–based design, one or more TLPs combine to form a transaction, which is transmitted over a link from one device on the bus to another. For a given TLP, a device provides device-level error detection and correction through analysis of reliability mechanisms present in every TLP. These error detection/correction responsibilities span the three functional device layers.
Read the full PCI Express* White Paper.
