Intel E7525 Memory Controller Hub: Datasheet
This document details the system architecture supported by the Intel® E7525 MCH, its external interfaces, and other features visible to hardware and software designers implementing a E7525 platform. Included in this specification are descriptions and pin listings for all external electrical interfaces, and descriptions of supported chipset components.
Intel® E7525 MCH system architecture
The architecture of the chipset provides the performance and feature set required for dual-processor based workstations. To accomplish this, the MCH has numerous reliability and manageability features on multiple interfaces. Detailed descriptions of the interfaces and feature set are provided in Chapter 5, “Functional Description.”
The chipset consists of the following components: Memory Controller Hub (MCH), ICH and the Intel® 6700PXH PCI-X Hub. Although a brief overview is provided here, detailed component information can be found in each device's respective documentation.
Intel® Xeon™ Processor with 800 MHz system Bus
The MCH supports either single or dual population of the Xeon processors. The front side bus supports a base system bus frequency of 200 MHz. The address and request interface is double pumped to 400 MHz while the 64-bit data interface (+ parity) is quad pumped to 800 MHz. This provides a matched system bus address and data bandwidths of 6.4 GB/s.
The MCH provides an integrated memory controller for direct connection to two channels of registered DDR333 or DDR2-400 memory. Peak theoretical memory data bandwidth using DDR333 technology is 5.33 GB/S. For DDR2-400 technology, this increases to 6.4 GB/s.
Read the full Intel E7525 Memory Controller Hub Datasheet.