Intel E7520 Memory Controller Hub: Datasheet
This document details the system architecture supported by the Intel® E7520 MCH, its external interfaces, and other features visible to hardware and software designers implementing a E7520 platform. Included in this specification are descriptions and pin listings for all external electrical interfaces, descriptions of internal registers, and descriptions of the MCH.
Intel® E7520 MCH System Architecture
The architecture of the MCH provides the performance and feature set required for dual processor-based volume to performance servers, with configuration options facilitating optimization of the platform for workloads characteristic of communication, presentation, storage, performance computation, or database applications. To accomplish this, the MCH has numerous RASUM (Reliability, Availability, Serviceability, Usability and Manageability) features on multiple interfaces. Detailed descriptions of the interfaces and RASUM features are provided in Chapter 5, “Functional Description”.
The MCH consists of the following components: Memory Controller Hub (MCH), ICH, and the Intel® 6700PXH 64-bit PCI Hub. Although a brief overview is provided here, detailed component information can be found in each device's respective documentation. 1.3.1 64-bit Intel® Xeon™ processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions)
The MCH supports either single or dual population of the Xeon processors. The front side bus supports a base system bus frequency of 200 MHz. The address and request interface is double pumped to 400 MHz while the 64-bit data interface (+ parity) is quad pumped to 800 MHz. This provides a matched system bus address and data bandwidths of 6.4 GB/s.
Read the full Intel® E7520 Memory Controller Hub Datasheet.