英特尔® E7505 芯片组内存控制器集线器数据表

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Intel® E7505 Chipset Memory Controller Hub Datasheet

The Intel® E7505 chipset is a high-performance chipset designed as the next generation workstation. The main components of the chipset are the Memory Controller Hub (MCH) host bridge and the Intel® 82801BA I/O Controller Hub 4 (ICH4) for the I/O subsystem. A supporting component for the platform is the Intel® 82870P2 PCI-64 Hub 2 (P64H2) for I/O expansion.

The MCH is supports the Intel® Xeon™ processor with 512-KB L2 cache and the Intel® Xeon™ processor with 533 MHz system bus in dual-processor mode. Four-way processor mode is not supported by the MCH. The MCH supports up to 16 GB of Double Data Rate (DDR) SDRAM system memory and provides the next generation AGP 8x graphics port.

This document describes the E7505 chipset MCH. The MCH signals, registers, DC electrical characteristics, ballout, package dimensions, and component testability are covered. The major functional blocks of the MCH are described. For detailed descriptions of other chipset components, refer to the respective component’s datasheet.

Intel® E7505 Chipset System Architecture

The Intel® E7505 chipset is optimized for the Intel® Xeon™ processor with 512 KB L2 cache. The architecture of the chipset provides the performance and feature-set required for dual-processor based workstations in the volume and performance market segments. The MCH supports AGP 8x with backwards compatibility to AGP 4x. The AGP interface is fully compliant with the AGP Specification 3.0. The system bus, used to connect the processor with the Intel® E7505 chipset, utilizes a 400 MHz/533 MHz transfer rate for data transfers, delivering a bandwidth of 4.27 GB/s.

Read the full Intel® E7505 Chipset Memory Controller Hub Datasheet.