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Intel® E7205 Chipset Memory Controller Hub Datasheet
Introduction The Intel® E7205 chipset is a high-performance chipset designed as the next generation workstation. The main components of the chipset are the Memory Controller Hub (MCH) host bridge and the Intel® 82801BA I/O Controller Hub 4 (ICH4) for the I/O subsystem. The MCH is designed to support the Intel® Pentium® 4 processor with 512-KB L2 cache on 0.13 micron process. Two and 4-way processor modes are not supported by the MCH. The MCH supports up to 4 GB of Double Data Rate (DDR) SDRAM system memory and provides the next generation AGP 8x graphics port. This document describes the E7205 chipset MCH. The MCH signals, registers, DC electrical characteristics, ballout, package dimensions, and component testability are covered. The major functional blocks of the MCH are described. For detailed descriptions of other chipset components, refer to the respective component’s datasheet Intel® E7205 Chipset System ArchitectureThe Intel® E7205 chipset is optimized for the Intel® Pentium® 4 processor with 512-KB L2 cache on 0.13 micron process. The system bus, used to connect the processor with the Intel® E7205 chipset, uses a 400 MHz/533 MHz transfer rate for data transfers, delivering a bandwidth of 4.27 GB/s. The Intel® E7205 chipset architecture supports a 144-bit wide, 266 MHz Double Data Rate (DDR) memory interface also capable of transferring data at 4.27 GB/s (see Table 1-1). The memory interface supports a dual channel DDR system memory with unbuffered SDRAM DIMMs only. The MCH supports AGP 8x with backwards compatibility to AGP 4x.
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