英特尔® 852GM 和英特尔® 82801DB I/O 控制器集线器嵌入式平台

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Intel® 852GM Chipset, Intel® 82801DB I/O Controller Hub Embedded Platform
Intel® Celeron® Processor on 0.13 Micron Process in 478-Pin Package, Mobile Intel® Celeron® Processor on 0.13 Micron Process and in Micro-FCPGA Package, and Intel® Celeron® M Processor: Platform Design Guide. This design guide provides Intel’s design recommendations for the Intel® 852GM chipset-based systems. These design guidelines have been developed to ensure maximum flexibility for board designers while reducing the risk of board-related issues. The following processors can be combined with the 852GM GMCH chipset: • Mobile Intel® Celeron® processor • Intel® Celeron® processor • Intel® Celeron® M processor
System overview
In addition to providing PCB design recommendations such as layout and routing guidelines, this document also addresses other design concerns such as power delivery. The reference schematic checklist included in this document may be used as reference for board designers. While the reference schematic checklist covers specific designs, the core schematics will remain the same for most 852GM chipset family platforms. The Intel® 852GM chipset is a Graphics Memory Controller Hub (GMCH) component for embedded platforms. It provides the processor interface, system memory interface (DDR SDRAM), hub interface, CRT interface, LVDS interface, and a DVO interface. The Intel 852GM GMCH and Intel® 82801DB I/O Controller Hub 4 (ICH4) is optimized for the Intel® Celeron® Processor, Mobile Intel® Celeron® Processor, or the Intel Celeron® M Processor. The accelerated hub architecture interface (the chipset component interconnect) is designed into the chipset to provide an efficient, high-bandwidth communication channel between the GMCH and the ICH4. An ACPI-compliant Intel 852GM chipset embedded platform may support the Full-On (S0), Power On Suspend (S1-M), Suspend to RAM (S3), Suspend to Disk (S4), and Soft-Off (S5) power management states. Through the use of an appropriate LAN device, the chipset also supports wake on LAN for remote administration and troubleshooting. The chipset architecture removes the requirement for the ISA expansion bus that was traditionally integrated into the I/O subsystem of PCIsets/AGPsets. This removes many of the conflicts experienced when installing hardware and drivers into legacy ISA systems. The elimination of ISA provides true plug-and-play for the platform. Traditionally, the ISA interface was used for audio and modem devices. The addition of AC’97 allows the OEM to use software-configurable AC’97 audio and modem coder/decoders (codecs) instead of the traditional ISA devices.
Read the full Chipset and I/O Controller Hub Embedded Platform Design Guide.